Ch16p

Chapter 16
Exercise Solutions

EX16.1
( 3.9 ) (8.85 ×10−14 )
COX = = 1.726 ×10−7 F / cm 2
200 × 10−8
2 (1.6 × 10−19 ) (11.7 ) ( 8.85 ×10 −14 )(1015 ) 1
γ = = 0.1055 V 2
1.726 × 10−7
ΔVTN = r ⎡ 0.576 + VSB − 0.576 ⎤ = ( 0.1055 ) ⎡ 0.576 + 5 + 0.576 ⎤
⎣ ⎦ ⎣ ⎦
ΔVTN = 0.169 V

EX16.2
(a)
vo = VDD − I D RD
⎛ k′ ⎞⎛ W ⎞
vo = 3 − ⎜ n ⎟ ⎜ ⎟ ⎣ 2 ( 3 − 0.5 ) vo − vo ⎦ RD
⎡ ⎤
2

⎝ 2 ⎠⎝ L ⎠
vo = 0.1
⎛ 0.06 ⎞ ⎡
⎟ ( 5 ) ⎣( 5 )( 0.1) − ( 0.1) ⎤ RD
2
0.1 = 3 − ⎜
⎝ 2 ⎠ ⎦
0.1 = 3 − 0.0735RD
RD = 39.5 K
(b)
⎛ 0.06 ⎞
⎟ ( 5 )( 39.5 )(VIt − 0.5 ) + (VIt − 0.5 ) − 3 = 0
2
⎜
⎝ 2 ⎠
5.925 (VIt − 0.5 ) + (VIt − 0.5 ) − 3 = 0
2

−1 ± 1 + 4 ( 5.925 )( 3)
(VIt − 0.5 ) = VOt =
2 ( 5.925 )
VOt = 0.632 V
VIt = 1.132 V

EX16.3
(a)
(i)
vo = VDD − VTNL = 3 − 0.4
vo = 2.6 V
(ii)
⎛W ⎞ ⎛W ⎞
⎜ ⎟ ⎡ 2 ( vI − 0.4 ) vo − vo ⎤ = ⎜ ⎟ [VDD − vo − 0.4]
2 2
⎣ ⎦
⎝ L ⎠D ⎝ L ⎠L
16 ⎡ 2 ( 2.6 − 0.4 ) vo − vo ⎤ = 2 [3 − vo − 0.4]
2 2
⎣ ⎦
35.2vo − 8vo = 6.76 − 5.2vo + vo
2 2

9vo − 40.4vo + 6.76 = 0
2

40.4 ± 1632.16 − 4 ( 9 )( 6.76 )
vo =
2 (9)
vo = 0.174 V

(b)
⎛ 60 ⎞
iD = ⎜ ⎟ (2) [3 − 0.174 − 0.4]
2

⎝ 2 ⎠
iD = 353.1 μ A
P = iD ⋅ VDD = 1.06 mW

EX16.4
(a)
⎛W ⎞ ⎛W ⎞
⎜ ⎟ ⎡ 2 ( vI − 0.4 ) vo − vo ⎤ = ⎜ ⎟ ( − ( −0.8 ) )
2 2

⎝ L ⎠D ⎣ ⎦
⎝ L ⎠L
6 ⎡ 2 ( 3 − 0.4 ) vo − vo ⎤ = 2 ( 0.64 )
⎣
2
⎦
6vo − 31.2vo + 1.28 = 0
2

31.2 ± 973.44 − 4 ( 6 )(1.28 )
vo =
2(6)
vo = 41.4 mV
(b)
⎛W ⎞ ⎛W ⎞
⎜ ⎟ ( vIt − 0.4 ) = ⎜ ⎟ ( −(−0.8) )
2 2

⎝ L ⎠D ⎝ L ⎠L
6 ( vIt − 0.4 ) = 2 ( 0.64 )
2

⇒ vIt = 0.862 V ⎫
⎬ Driver
vOt = 0.862 − 0.4 = 0.462 V ⎭
vIt = 0.862 V ⎫
⎬ Load
vOt = VDD + VTNL = 3 − 0.8 = 2.2 V ⎭
(c)
⎛ 60 ⎞
iD = ⎜ ⎟ (2) ( − ( −0.8 ) ) = 38.4 μ A
2

⎝ 2 ⎠
P = iD ⋅ VDD = 115.2 μ W

EX16.5
We have
{
VOH = VDD − VTNLO + r ⎡ 2φ fP + VSB − 2φ fP ⎤
⎣ ⎦ }
{
VOH = 5 − 0.8 + 0.35 ⎡ 0.73 + VOH −
⎣ 0.73 ⎤}
⎦
VOH − 4.499 = −0.35 0.73 + VOH
Squaring both sides
VOH − 8.998VOH + 20.241 = 0.1225(0.73 + VOH )
2

VOH − 9.1205VOH + 20.15 = 0
2

9.1205 ± 83.1835 − 4(20.15)
VOH =
2
VOH = 3.76 V

EX16.6
a.
i. A = logic 1 = 10 V, B = logic 0 “A” driver in nonsaturation. “B” driver off

′
⎛ kn ⎞ ⎛ W ⎞ ⎛ k′ ⎞⎛ W ⎞
⎜ 2 ⎟ ⎜ L ⎟ ( −VTNL ) = ⎜ 2 ⎟ ⎜ L ⎟ ⎡ 2 ( vI − vTND ) VOL − VOL ⎤
2 2
⎣ ⎦
⎝ ⎠ ⎝ ⎠L ⎝ ⎠ ⎝ ⎠D
2 ( 3) = (10 ) ⎡ 2 (10 − 1.5 ) V0 L − V02L ⎤
2
⎣ ⎦
9 = 5 (17V0 L − V02L )
5V02L − 85V0 L + 9 = 0

(85 ) − 4 ( 5 )( 9 )
2
85 ±
V0 L = ⇒ V0 L = 0.107 V
2(5)
ii. A = B = logic 1
′
⎛ kn ⎞ ⎛ W ⎞ ⎛ k′ ⎞⎛ W ⎞
⎜ 2 ⎟ ⎜ L ⎟ ( −VTNL ) = 2 ⎜ 2 ⎟ ⎜ L ⎟ ⎣ 2 ( vI − vTND )VOL − VOL ⎤
⎡
2 2
⎦
⎝ ⎠ ⎝ ⎠L ⎝ ⎠ ⎝ ⎠D
2 ( 3) = ( 2 )(10 ) ⎡ 2 (10 − 1.5 ) V0 L − V02L ⎤
2
⎣ ⎦
9 = 10 (17V0 L − V02L )
10V02L − 170V0 L + 9 = 0

(170 ) − 4 (10 )( 9 )
2
170 ±
V0 L = ⇒ V0 L = 0.0531 V
2 (10 )
b. Both cases.
35
iD = ⋅ ( 2 )( 3) = 315 μ A ⇒ P = iD ⋅ VDD ⇒ P = 3.15 mW
2

2

EX16.7
800
P = iD ⋅ VDD ⇒ iD = = 160 μ A
5
35 ⎛ W ⎞ ⎛W ⎞ ⎛W ⎞
iD = 160 = ⋅ ⎜ ⎟ (1.4 ) = 34.3 ⎜ ⎟ ⇒ ⎜ ⎟ = 4.66
2

2 ⎝ L ⎠L ⎝ L ⎠L ⎝ L ⎠L
35 ⎛ W ⎞ ⎡ ⎛W ⎞
⋅ ⎜ ⎟ 2 ( 5 − 0.8 )( 0.12 ) − ( 0.12 ) ⎤ ⇒ ⎜ ⎟ = 9.20
2
iD = 160 =
2 ⎝ L ⎠D ⎣ ⎦ ⎝ L ⎠D

EX16.8
VDD 2.1
(a) VIt = = = 1.05 V
2 2
VOPt = VIt − VTD = 1.05 − (−0.4) = 1.45 V
VONt = VIt − VTN = 1.05 − 0.4 = 0.65 V
2.1 + (−0.4) + 0.5(0.4)
(b) VIt = = 1.16 V
1 + 0.5
VOPt = 1.16 + 0.4 = 1.56 V
VONt = 1.16 − 0.4 = 0.76 V
2.1 + (−0.4) + 2(0.4)
(c) VIt = = 0.938 V
1+ 2
VOPt = 0.938 + 0.4 = 1.338 V
VONt = 0.538 V

EX16.9

P = f ⋅ CL ⋅ VDD
2

( 0.10 ×10 ) = f ( 0.5 ×10 ) ( 3)
−6 −12 2

f = 2.22 × 104 Hz ⇒ f = 22.2 kHz

EX16.10
a.
10 − 2 + 2.5(2)
K n / K p = 200 / 80 = 2.5 ⇒ VIt = ⇒ VIt = 4.32 V
1 + 2.5
V0 Pt = 6.32 V
V0 Nt = 2.32 V
b.
10 − 2 − 2 ⎡ 2.5 ⎤
VIL = 2 + ⋅ ⎢2 − 1⎥ ⇒ VIL = 3.39 V
2.5 − 1 ⎣ 2.5 + 3 ⎦
1
V0 HU = {(1 + 2.5)(3.39) + 10 − (2.5)(2) + 2}
2
V0 HU = 9.43 V
10 − 2 − 2 ⎡ 2(2.5) ⎤
VIH = 2 + ⋅⎢ − 1⎥ ⇒ VIH = 4.86 V
2.5 − 1 ⎢ 3(2.5) + 1 ⎥
⎣ ⎦
(4.86)(1 + 2.5) − 10 − (2.5)(2) + 2
V0 LU =
2(2.5)
V0 LU = 0.802 V
c.
NM L = VIL − V0 LU = 3.39 − 0.802 ⇒ NM L = 2.59 V
NM H = V0 HU − VIH = 9.43 − 4.86 ⇒ NM H = 4.57 V

EX16.11
3 PMOS in series and 3 NMOS in parallel.
Worst Case: Only one NMOS is ON in Pull-down mode ⇒ same as the CMOS inverter ⇒ Wn = W .
All 3 PMOS are on during pull-up mode ⇒ W p = 3(2W ) = 6W .

EX16.12
NMOS: Worst Case, M NA , M NB on, Wn = 2(W ) or M NC , M ND or M NC , M NE on ⇒ Wn = 2(W ).
PMOS: M PA and M PC on or M PA and M PB on ⇒ WP = 2(2W ) = 4W
If M PD and M PE on, need WP = 2(4W ) = 8W

EX16.13
a. vI = φ = 5 V ⇒ v0 = 4 V
b. vI = 3 V, φ = 5 V ⇒ v0 = 3 V
c. vI = 4.2 V, φ = 5 V ⇒ v0 = 4 V
d. vI = 5 V, φ = 3 V ⇒ v0 = 2 V

EX16.14
(a) vI = 8V , φ = 10V ⇒ vGSD = 8 V
M D in nonsaturation

K D ⎡ 2(vGSD − VTND )vO − vO ⎤
⎣
2
⎦
K L [VDD − vO − VTNL ]
2

KD ⎡ K
2 ( 8 − 2 )( 0.5 ) − ( 0.5 ) ⎤ = [10 − 0.5 − 2] ⇒ D = 9.78
2 2

KL ⎣ ⎦ KL
(b)
vI = φ = 8V ⇒ vGSD = 6 V
KD ⎡ K
2 6 − 2 )( 0.5 ) − ( 0.5 ) ⎤ = [10 − 0.5 − 2] ⇒ D = 15
⎣ (
2 2

KL ⎦ KL

EX16.15
16 K ⇒ 16384 cells
Total Power = 125 mW = (2.5) IT ⇒ IT = 50 mA
50 mA
Then, for each cell, I = ⇒ I = 3.05 μ A
16384
VDD V 2.5
Now, I ≅ or R = DD = ⇒ R = 0.82 M Ω
R I 3.05

TYU16.1
750
P = iD ⋅ VDD ⇒ iD = = 150 μ A
5
35 ⎛ W ⎞
150 = ⎜ ⎟ (5 − 0.2 − 0.8)
2

2 ⎝ L ⎠L
⎛W ⎞ ⎛W ⎞
150 = 280 ⎜ ⎟ ⇒ ⎜ ⎟ = 0.536
⎝ L ⎠L ⎝ L ⎠L
⎛ k′ ⎞⎛ W ⎞
iD = ⎜ n ⎟ ⎜ ⎟ ⎡ 2(vI − VTND )vO − vO ⎤
2

⎝ 2 ⎠ ⎝ L ⎠D ⎣ ⎦
35 ⎛ W ⎞
150 = ⎜ ⎟ ⎡ 2(4.2 − 0.8)(0.2) − (0.2) 2 ⎤
2 ⎝ L ⎠D ⎣ ⎦

⎛W ⎞ ⎛W ⎞
150 = 23.1 ⋅ ⎜ ⎟ ⇒ ⎜ ⎟ = 6.49
⎝ L ⎠D ⎝ L ⎠D

TYU16.2
350
P = iD ⋅ VDD ⇒ I D = = 70 μ A
5
⎛ k′ ⎞⎛ W ⎞
iD = ⎜ n ⎟ ⎜ ⎟ ( −VTNL )
2

⎝ 2 ⎠ ⎝ L ⎠L
35 ⎛ W ⎞ ⎛W ⎞
70 = ⋅ ⎜ ⎟ ( 2 ) ⇒ ⎜ ⎟ = 1
2

2 ⎝ L ⎠L ⎝ L ⎠L
35 ⎛ W ⎞ ⎡
⋅ ⎜ ⎟ 2 ( 5 − 0.8 )( 0.05 ) − ( 0.05 ) ⎤
2
iD =
2 ⎝ L ⎠D ⎣ ⎦
⎛W ⎞ ⎛W ⎞
70 = 7.31 ⋅ ⎜ ⎟ ⇒ ⎜ ⎟ = 9.58
⎝ L ⎠D ⎝ L ⎠D

TYU16.3

800
P = iD ⋅ VDD ⇒ iD = = 160 μ A
5
35 ⎛ W ⎞ ⎛W ⎞
iD = 160 = ⋅ ⎜ ⎟ (1.4 ) ⇒ ⎜ ⎟ = 4.66
2

2 ⎝ L ⎠L ⎝ L ⎠L
35 1 ⎛ W ⎞ ⎡ ⎛W ⎞
iD = 160 μ A = ⋅ ⋅ ⎜ ⎟ 2 ( 5 − 0.8 )( 0.12 ) − ( 0.12 ) ⎤ ⇒ ⎜ ⎟ = 27.6
2

2 3 ⎝ L ⎠D ⎣ ⎦ ⎝ L ⎠D

TYU16.4
a. From the load transistor:
⎛ ′
kn ⎞ ⎛ W ⎞ 35
I DL = ⎜ ⎟ ⎜ ⎟ (VGSL − VTNL ) = ( 0.5 )( 5 − 0.15 − 0.7 )
2 2

⎝ 2 ⎠ ⎝ L ⎠L 2
or
I DL = 150.7 μ A
Maximum v0 occurs when either A or B is high and C is high. For the two NMOS is series, the effective
k N is cut in half, so
1 ⎡⎛ k n ⎞ ⎛ W ⎞ ⎤
′
I DL = ⎢⎜ ⎟ ⎜ ⎟ ⎥ ⎡ 2 (VGSD − VTND ) VDS − VDS ⎤
2

2 ⎣⎝ 2 ⎠ ⎝ L ⎠ D ⎦ ⎣ ⎦
or
1 ⎡ 35 ⎛ W ⎞ ⎤ ⎡
⎢ ⋅ ⎜ ⎟ ⎥ 2 ( 5 − 0.7 )( 0.15 ) − ( 0.15 ) ⎤
2
150.7 =
2 ⎣ 2 ⎝ L ⎠D ⎦ ⎣ ⎦
which yields
⎛W ⎞
⎜ ⎟ = 13.6
⎝ L ⎠D
b. P = iD ⋅ VDD = (150.7 )( 5 ) ⇒ P = 753 μ W

TYU16.5
a. v0 (max) occurs when A = B = 1 and C = D = 0 or A = B = 0 and C = D = 1
⎛W ⎞ 1 ⎛W ⎞
⎜ ⎟ (−VTNL ) = ⋅ ⎜ ⎟ ⎡ 2(vI − VTND )vO − vO ⎤
2 2

⎝ L ⎠L 2 ⎝ L ⎠D ⎣ ⎦
1 ⎛W ⎞
⎡ ⎤
(0.5)(1.2)2 = ⋅ ⎜ ⎟ ⎣ 2(5 − 0.7)(0.15) − (0.15) 2 ⎦
2 ⎝ L ⎠D
⎛W ⎞ ⎛W ⎞
0.72 = (0.634) ⎜ ⎟ ⇒ ⎜ ⎟ = 1.14
⎝ L ⎠D ⎝ L ⎠D
b.
⎛ k′ ⎞⎛ W ⎞ ⎛ 35 ⎞
iD = ⎜ n ⎟ ⎜ ⎟ (−VTNL ) 2 = ⎜ ⎟ (0.5) [ −(−1.2) ]
2

⎝ 2 ⎠ ⎝ L ⎠L ⎝ 2⎠
iD = 12.6 μ A
P = iD ⋅ VDD = (12.6)(5) ⇒ P = 63 μ W

TYU16.6
a.
K n = K p = 50 μ A / V 2
VIt = 2.5 V
iD (max) = K n (VIt − VTN ) 2 = 50(2.5 − 0.8) 2 ⇒ iD (max) = 145 μ A

b.
K n = K p = 200 μ A / V 2
VIt = 2.5 V
iD (max) = (200)(2.5 − 0.8) 2 ⇒ iD (max) = 578 μ A

TYU16.7
a.
5 − 2 + (1)(0.8)
VIt =
1+1
VIt = 1.9 V
V0 Pt = 3.9 V
V0 Nt = 1.1 V
b.
3
VIL = 0.8 + ⋅ [5 − 2 − 0.8] ⇒ VIL = 1.63 V
8
1
V0 HU = {2(1.63) + 5 − 0.8 + 2}
2
V0 HU = 4.73 V
5
VIH = 0.8 + (5 − 2 − 0.8) ⇒ VIH = 2.18 V
8
1
V0 LU = {2(2.18) − 5 − 0.8 + 2}
2
V0 LU = 0.275 V
c.
NM L = VIL − V0 LU = 1.63 − 0.275 ⇒ NM L = 1.35 V
NM H = V0 HU − VIH = 4.73 − 2.18 ⇒ NM H = 2.55 V

TYU16.8

TYU16.9
NMOS − 2 transistors in series
Wn = 2 (W ) = 2W
PMOS − 2 transistors in series
W p = 2 ( 2W ) = 4W

TYU16.10
The NMOS part of the circuit is:

TYU16.11
The NMOS part of the circuit is:

TYU16.12
Exclusive-OR

A B f
0 0 0
1 0 1
0 1 1
1 1 0

TYU16.13

NMOS conducting for 0 ≤ vI ≤ 4.2 V
⇒ NMOS Conducting: 0 ≤ t ≤ 8.4 s
NMOS Cutoff: 8.4 ≤ t ≤ 10 s
PMOS cutoff for 0 ≤ vI ≤ 1.2 V
⇒ PMOS Cutoff: 0 ≤ t ≤ 2.4 s
PMOS Conducting: 2.4 ≤ t ≤ 10 s

TYU16.14
(a) 1 K ⇒ 32 × 32 array
Each row and column requires a 5-bit word ⇒ 6 transistors per row and column, ⇒ 32 × 6 + 32 × 6 = 384
transistors plus buffer transistors.
(b) 4 K ⇒ 64 × 64 array
Each row and column requires a 6-bit word ⇒ 7 transistors per row and column ⇒ 64 × 7 + 64 × 7 = 896
transistors plus buffer transistors.
(c) 16 K ⇒ 128 × 128 array
Each row and column requires a 7-bit word ⇒ 8 transistors per row and column
⇒ 128 × 8 + 128 × 8 = 2048 transistors plus buffer transistors.

TYU16.15
From Equation (16.84)
(W / L )nA 2 (VDDVTN ) − 3VTN 2(2.5)(0.4) − 3(0.4) 2
2

= = = 0.526
(W / L )n1 (VDD − 2VTN )
2
( 2.5 − 2(0.4) )
2

From Equation (16.86)

(W / L ) p kn 2 (VDDVTN ) − 3VTN
′ 2
⎡ 2(2.5)(0.4) − 3(0.4) 2 ⎤
= ⋅ = (2.5) ⎢ ⎥ = 0.862
(W / L )nB k′
p (VDD + VTP )
2
⎣ (2.5 − 0.4) 2 ⎦
⎛W ⎞ ⎛W ⎞
So ⎜ ⎟ of transmission gate device must be < 0.526 times the ⎜ ⎟ of the NMOS transistors in the
⎝ L⎠ ⎝L⎠
⎛W ⎞ ⎛W ⎞
inverter cell. The ⎜ ⎟ of the PMOS transistors must be < 0.862 times the ⎜ ⎟ of the transmission gate
⎝L⎠ ⎝L⎠
⎛ W⎞ ⎛ W⎞
devices. Then the ⎜ ⎟ of the PMOS devices must be < 0.453 times ⎜ ⎟ of NMOS devices in cell.
⎝L⎠ ⎝L⎠

TYU16.16
Initial voltage across the storage capacitor = VDD − VTN = 3 − 0.5 = 2.5 V .
Now
dV I
−I = C or V = − ⋅ t + K
dt C
2.5
where K = 2.5 V , t = 1.5 ms, V = = 1.25 V , and C = 0.05 pF . Then
2
I (1.5 × 10−3 )
1.25 = 2.5 − ⇒
(0.05 × 10−12 )
I = 4.17 × 10−11 A ⇒ I = 41.7 pA

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