SlideShare a Scribd company logo
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
DOI : 10.5121/vlsic.2015.6102 9
DYNAMIC FLOATING OUTPUT STAGE FOR
LOW POWER BUFFER AMPLIFIER FOR LCD
APPLICATION
Hari shanker srivastava and Dr.R.K Baghel
Department of Electronics and Communication
MANIT Bhopal
ABSTRACT
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating
current node is used at the output of two-stage amplifier to increase the charging and discharging of
output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to
support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current
of 5 µA for 30 pF capacitance, the settling time calculated as 4.5µs, the slew rate obtained as 5V/µs and
area on chip is 30×72µ݉ଶ
.
KEYWORDS
Liquid crystal display (LCD) ,column driver, row driver, gamma correction, class AB output stage
1. INTRODUCTION
With increasing demand of low-power portable LCD panel there was hard-core research to
develop it as with the low-power means we have to decrease the static loss of the component or
the blocks used in the driving scheme of the LCD panel, the driving scheme of LCD panel is
shown in figure 1, which consists of source driver circuits (column driver), gate driver
circuits(row driver), the reference voltages, timing controller's, gamma correction circuits,
column driver is used to drive a pixel with required colored information and row driver used to
refresh a pixel which required refreshing rate.[1,2] The column driver as shown in fig.2 contains
input registers, shift registers, level shifters, digital to analog converter and buffer amplifiers. The
column driver which is important to achieve the high resolution, high-speed, and low power
dissipation among these output buffers is the key to determine the speed, resolution, and power
consumption each pixel is derived by a buffer amplifier which is either positive polarity or
negative polarity to drive the alternate pixel.
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
10
Fig 1.Block diagram of LCD panel
Fig 2.Column driver architecture of LCD
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
11
Fig 3.Architecture of an R_DAC based column
Fig 4. Dot inversion method to drive
There are four driving schemes for LCD panels these are row inversion, column inversion, frame
inversion and dot inversion method, dot inversion method is best to drive a particular pixel to
remove cross talk figure.4 shows its driving scheme adjacent pixel is driven by either a positive
polarity buffer or by negative polarity buffer with due respect to common voltage, this will
improve the lifetime of the liquid crystal.[3],[4],[5].The figure.4 shows a driving method of
column driver to drive a pixel each adjacent pixels are driven by positive and negative polarity
buffer [8-11].
In proposed buffer amplifier a single buffer which contain NMOS & PMOS differential pair,
PMOS buffer has large discharge capability and NMOS has large charge capability are used to
drive the adjacent pixel to follow the dot inversion technique. A floating output stage is used to
control the biasing current of output stage using aspect ratio of MOS used in output stage.
2. FREQUENCY ANALYSIS OF TWO STAGE BUFFER
To drive high capacitive and resistive load of the pixel a class AB output stage is best suited for
the column driver line. For low offset voltage we need high open loop gain of buffer amplifier,
two-stage amplifier are generally used to drive the pixel, amplifier requires compensation
capacitor for the stability as the phase margin of the operation amplifier depend upon the
compensation capacitor, the slew rate is also depends on compensation capacitor. As some
buffers adopt output node to get the stability without using Miller capacitance, some uses charge
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
12
conservation technique to reduce the dynamic power loss without Miller capacitance. These
buffer suffers from charge storage problem as during scanning off time of row driver's the
columns lines are for a small duration of time is isolated from the pixels to refresh formation at
buffer quickly, so we need a capacitor which is fulfilled by compensation capacitor so those
buffers which are without compensation capacitors have a problem that they can't refresh there
information within the refresh time. As the proposed buffer has two-stage with the Miller
capacitor for the compensation is used in design. The figures.5 shows the equivalent circuit of
two stage operational amplifier with output load resistance and capacitance.
ࡾࡸ
࡯ࡸ
Fig 5. Small signal model of proposed buffer amplifier
Figure 5 shows small signal equivalent diagram of proposed amplifier for two stage under open
loop, ݃௠ଵ & ݃௠ଶ are the transconductance, ܴଵ & ܴଶ are the output resistance, ‫ܥ‬ଵ & ‫ܥ‬ଶ are the
open loop parasitic capacitance of the first and second stages, ‫ܥ‬௖ is the miller capacitance for
phase compensation and ܴ௅& ‫ܥ‬௅are the resistive and capacitive load.
The transfer function of the amplifier is calculated using current equation:-
using current equation at input node:
݃௠ଵܸ௜ௗ +
ܸଵ
ܴଵ
+ ܵ‫ܥ‬ଵܸଵ + ሺܸଵ − ܸ଴ሻܵ‫ܥ‬஼ = 0
ܸଵ ቂ
ଵ
ோభ
+ ܵሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻቃ = ܸܵ଴‫ܥ‬஼ − ݃௠ଵܸ௜ௗ (1)
using current equation at output node:
݃௠ଶܸଵ +
ܸ଴
ܴଶ
+ ܵ‫ܥ‬ଶܸ଴ + ሺܸ଴ − ܸଵሻܵ‫ܥ‬஼ +
ܸ଴
ቀܴ௅ +
1
ܵ‫ܥ‬௅
ቁ
= 0
ܸ଴ ൤
1
ܴଶ
+ ܵሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ +
ܵ‫ܥ‬௅
1 + ܴܵ௅‫ܥ‬௅
൨ = ܸଵሺܵ‫ܥ‬஼ − ݃௠ଶሻ ሺ2ሻ
Put value of ܸଵfrom equation 1 to equation 2 we get,
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
13
ܸ଴
ܸ௜ௗ
=
݃௠ଵ݃௠ଶܴଵܴଶ ൬1 −
ܵ‫ܥ‬஼
݃௠ଶ
൰ሺ1 + ܴܵ௅‫ܥ‬௅ሻ
1 + ‫ܣ‬ଵܵ + ‫ܣ‬ଶܵଶ + ‫ܣ‬ଷܵଷ
ሺ3ሻ
‫ܣ‬ଵ = ܴଵሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ + ܴ௅‫ܥ‬௅ + ܴଶሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ + ‫ܥ‬௅ܴଶ + ܴଵܴଶ݃௠ଶ‫ܥ‬஼
‫ܣ‬ଶ = ܴଵܴ௅‫ܥ‬௅ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ + ܴଵܴଶሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ + ܴଵܴଶ‫ܥ‬௅ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ + ‫ܥ‬௅ܴ௅ܴଶሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ
+ ܴଵܴଶ‫ܥ‬஼ሾ‫ܥ‬஼ − ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ݃௠ଶܴଵሿ
‫ܣ‬ଷ = ܴଵܴଶܴ௅‫ܥ‬௅ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ + ܴଵ
ଶ
ܴଶ‫ܥ‬஼
ଶ
ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ
As from equation 3 it show 3rd order transfer function
‫ܣ‬଴ሺܵሻ =
‫ܣ‬ௗ௖ ቀ1 +
ܵ
߱௓ଵ
ቁ ቀ1 +
ܵ
߱௓ଶ
ቁ
ቀ1 +
ܵ
߱௉ଵ
ቁ ቀ1 +
ܵ
߱௉ଶ
ቁ ቀ1 +
ܵ
߱௉ଷ
ቁ
to solve the 3rd order transfer function using dominant pole concept, the characteristic equation is
written as:
1 + ‫ܣ‬ଵܵ + ‫ܣ‬ଶܵଶ
+ ‫ܣ‬ଷܵଷ
= 0
≈ ‫ܣ‬ଵܵ + ‫ܣ‬ଶܵଶ
+ ‫ܣ‬ଷܵଷ
= 0
≈ ‫ܣ‬ଵܵሺ1 +
‫ܣ‬ଶ
‫ܣ‬ଵ
ܵ +
‫ܣ‬ଷ
‫ܣ‬ଵ
ܵଶ
ሻ = 0
߱௉ଵ ≅ −
1
‫ܣ‬ଵ
߱௉ଶ ≅
‫ܣ‬ଵ
‫ܣ‬ଶ
߱௉ଷ =
1
ܲଶ
‫ܣ‬ଵ
‫ܣ‬ଶ
‫ܣ‬ௗ௖ = ݃௠ଵ݃௠ଶܴଵܴଶ
߱௉ଵ ≅
1
ܴଵܴଶ݃௠ଶ‫ܥ‬஼ + ‫ܥ‬௅ܴଶ
߱௉ଶ ≅
1
ሾሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻܴ௅ሿ
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
14
߱௉ଷ ≅
݃௠ଶ‫ܥ‬஼ +
‫ܥ‬௅
ܴଵ
ൗ
‫ܥ‬஼‫ܥ‬௅
߱௓ଵ =
ି௚೘మ
஼಴
and ߱௓ଶ =
ଵ
ோಽ஼ಽ
the unity gain frequency(߱௧)= ‫ܣ‬ௗ௖ ߱௉ଵ
߱௧ =
݃௠ଵ݃௠ଶ
‫ܥ‬஼݃௠ଶ +
‫ܥ‬௅
ܴଵ
ൗ
taking 3rd pole very far away from unity gain bandwidth so it does not affect the phase margin
so ߱௓ଶ will compensate for ߱௉ଷ so the transfer function act like 2nd order transfer function,
‫ܣ‬଴ሺܵሻ =
‫ܣ‬ௗ௖ ቀ1 +
ܵ
߱′௓ଵ
ቁ
ቀ1 +
ܵ
߱′௉ଵ
ቁ ቀ1 +
ܵ
߱′௉ଶ
ቁ
where ߱′௓ଵ =
ି௚೘మ
஼಴
߱′௉ଵ ≅
1
ܴଵܴଶ݃௠ଶ‫ܥ‬஼
߱௉ଶ ≅
݃௠ଶ
ሾ‫ܥ‬ଶሿ
Phase margin of the amplifier is as:
< ‫ܣ‬଴ሺܵሻ = ‫݊ܽݐ‬ିଵ
൬
߱
߱′௓ଵ
൰ − ‫݊ܽݐ‬ିଵ
൬
߱
߱′௉ଵ
൰ − ‫݊ܽݐ‬ିଵ
൬
߱
߱′௉ଶ
൰
as ω=GBW(taken this as a frequency range)
< ‫ܣ‬଴ሺܵሻ = −‫݊ܽݐ‬ିଵ
൬
GBW
߱′௓ଵ
൰ − ‫݊ܽݐ‬ିଵ
൬
GBW
߱′௉ଵ
൰ − ‫݊ܽݐ‬ିଵ
൬
GBW
߱′௉ଶ
൰
under condition ߱′௓ଵ ≥ 10‫ܹܤܩ‬
< ‫ܣ‬଴ሺܵሻ = ‫݊ܽݐ‬ିଵ
൬
GBW
߱′௓ଵ
൰ − ‫݊ܽݐ‬ିଵሺ‫ܣ‬ௗ௖ ሻ − ‫݊ܽݐ‬ିଵ
൬
GBW
߱′௉ଶ
൰
as ‫ܣ‬ௗ௖ is very higher value so ‫݊ܽݐ‬ିଵሺ‫ܣ‬ௗ௖ ሻ=90଴
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
15
< −180଴
− ܲ‫ܯ‬ = ‫݊ܽݐ‬ିଵ
൬
1
10
൰ − 90଴
− ‫݊ܽݐ‬ିଵ
൬
GBW
߱′௉ଶ
൰
PM=90଴
-‫݊ܽݐ‬ିଵ
ቀ
ୋ୆୛
ఠ′ುమ
ቁ − ‫݊ܽݐ‬ିଵ
ቀ
ୋ୆୛
ఠ′ೋభ
ቁ
For phase margin of 60଴
and ߱′௓ଵ = 10‫ܹܤܩ‬
߱′௉ଶ = 2.2 ‫ܹܤܩ‬ ߱′௉ଶ = 2.2 ‫ܹܤܩ‬
‫ܥ‬஼ = .22‫ܥ‬௅ and ݃௠ଶ = 10݃௠ଵ
As seen that with higher value ݃௠ଶ the value of ‫ܥ‬஼ we will get become smaller but it leads to
large current flow in output stage and hence more static power loss occurs in amplifier as with
large value of ‫ܥ‬஼ it accurse large area on chip, if we chose load resistance and capacitance too
large than open loop zero come in picture and then,
PM=90଴
− ‫݊ܽݐ‬ିଵ
ቀ
ୋ୆୛
ఠ′ೋభ
ቁ then
௚೘మ
௚೘భ
=
ଵ
୲ୟ୬ሺଽ଴బି௉ெሻ
Fig 6. Open loop frequency response of two-stage opam with & without load capacitance and resistance
3. PROPOSED BUFFER AMPLIFIER WITH DYNAMIC FLOATING
To reduce the static power loss we combined N- type and P-type differential pair with dynamic
floating concept to reduce the current flowing at the output stage, two floating bias current ln1
and ln2 are used to charge and discharge the output node in combination with lb1 and lb2, during
transition phase from low to high Mp-bias will provide extra current to charge the capacitive load
and during high to low Mn-bias will sink the extra current to discharge the capacitive load
quickly this is the methodology for which we quickly charge and discharge the output load
without increasing the static current that flows through the complementary common source
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
16
amplifier M01 and M02. The two output are isolated by the combination of 6 transistors as shown
in the figure.7 Mn-bias, Mn-bias,MDN1, MDN2, MDP1 and MDP2 for same rising and falling
time ln1=ln2,lb1=lb2
lb1 = lb2 = ln1൤ 1 +
൫ௐ
௅ൗ ൯
ಾವಿమ
൫ௐ
௅ൗ ൯
ಾವಿభ
+
൫ௐ
௅ൗ ൯
ಾವುమ
൫ௐ
௅ൗ ൯
ಾವುభ
൨
The schematic of the proposed buffer is shown in the figure. 8,M1-M5 shows NMOS differential
pair,M6-M10 shows PMOS differential pair,C1-C4 shows miller capacitance, the biasing current
of NMOS and PMOS pair is Ib as M01 and M02 are mirrored from M5 and M10 which is Ib/2
current that will flow, as seen the output stage biased by dynamic floating and 2 single-stage
differential pair, the circuit will suffer from output DC offset voltage which is removed by proper
sizing as
൫ܹ
‫ܮ‬ൗ ൯
ெ଴ଵ
൫ܹ
‫ܮ‬ൗ ൯
ସ
=
൫ܹ
‫ܮ‬ൗ ൯
ெ଴ଶ
൫ܹ
‫ܮ‬ൗ ൯
ଽ
= ln1 ቎1 +
൫ܹ
‫ܮ‬ൗ ൯
ெ஽ேଶ
൫ܹ
‫ܮ‬ൗ ൯
ெ஽ேଵ
+
൫ܹ
‫ܮ‬ൗ ൯
ெ஽௉ଶ
൫ܹ
‫ܮ‬ൗ ൯
ெ஽௉ଵ
቏
To design operational amplifier for LCD the following requirement should meet according to
number of bits or resolution of DAC used in LCD panel[23],The open loop gain will be estimated
as
‫ܣ‬ை௅஽஼ ≥ 2ேାଵ
Fig 7. Architecture of proposed dynamic floating buffer amplifier
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
17
Let open loop gain will be 1000 then gain error will be
gain error =
ଵ
.ହ×ଵ଴଴଴
= .0002 ≤
௏ೝ೐೑
ଶಿశభ
so min value of VDD=512× .002 = 1.02 ‫ݐ݈݋ݒ‬ and with specific settling time which should be
less than scanning time let it will be 1µs,the gain bandwidth
‫ܹܤܩ‬ ≥
݈݊2ேାଵ
2ߨ‫ݐ‬௦
for 8 bit the frequency does not exceed 1Mhz. So the design specification for buffer amplifier is
DC gain ≥ 1000=60db, VDD=3.3 volt , GBW=1Mhz PM=60o
,CMOS technology 180nm,
load capacitance= 30pf and load resistance of 30kΩ.
Fig 8. Schematic of proposed dynamic floating buffer amplifier
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
18
M1 1.5
1ൗ M9 5
1ൗ M01 28
1ൗ
M2 1.9
1ൗ M10 5
1ൗ M02 28
1ൗ
M3 1.9
1ൗ MPBIAS 4.5
1ൗ C1 1p
M4 5
1ൗ MNBIAS 4
1ൗ C2 6p
M5 5
1ൗ MDN1 4.5
1ൗ C3 1p
M6 2
1ൗ MDN2 9
1ൗ C4 6p
M7 25
1ൗ MDP1 8
1ൗ CL 30P
M8 25
1ൗ MDP2 4
1ൗ RL 30Ω
4. EXPERIMENTAL RESULT
The proposed buffer amplifier is fabricated using a 180nm CMOS technology. The chip area
occupied by the buffer is 30×72 µ݉ଶ
, fig 9 shows the output with 50kz input square wave with
load capacitance of 30pF and 30kΩ resistance, fig 10 shows triangular response of proposed
buffer, the slew rate obtained is 4.8v/µs with setting time of 4.5 µs and 4.2 µs for up and down
stream of square wave, the biasing current per channel is 5µA. And power consumed by buffer is
72 µw. The simulation results using transient and AC analysis is shown in figure from 9 to15
using cadence spectre simulation tool.
5. CONCLUSION
This paper represents a low power buffer amplifier, with low quiescent current with the dynamic
floating output node we adjust the output bias current without changing the input differential pair
biasing current configuration, according to load capacitance the output current will be varied with
the help of floating bias current network. The use-fullness of such type of buffer is, it work as
positive and negative type buffer without any switched capacitor network which is used to toggle
the differential amplifier in between positive and negative buffer.
COMPARISON TABLE
This work [1] [2] [3] [4]
Process 180nm CMOS .35µmCMOS .35µmCMOS .35µm CMOS .35µm CMOS
VDD 3.3 5 3.3 5
Bias current 5µA/per channel 2µA 7.4µA NA 5µA
loads 30KΩ, 30pF 10KΩ, 24pF 600pF 400pF 10pF
o/p swing 96% NA NA NA NA
Settling time 4.5µs 2µs 8µs 1µs .5µs
Slew rate 5v/ µs NA NA NA 2v/ µs
Area 30×72 µ݉ଶ
22×190µ݉ଶ
100×45µ݉ଶ
86×74 µ݉ଶ
.04 m݉ଶ
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
Fig 9. Simulation result with rectangular wave of frequency 50khz with load
Fig 10. Simulation result with rectangular wave of frequency 50khz with two input output
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
Fig 9. Simulation result with rectangular wave of frequency 50khz with load
result with rectangular wave of frequency 50khz with two input output
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
19
result with rectangular wave of frequency 50khz with two input output
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
Fig 11. Simulation result with triangular wave of frequency 50khz with load
Fig 12. Simulation result with triangular wave of frequency 50khz with two input output
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
Fig 11. Simulation result with triangular wave of frequency 50khz with load
Fig 12. Simulation result with triangular wave of frequency 50khz with two input output
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
20
Fig 12. Simulation result with triangular wave of frequency 50khz with two input output
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
Fig 13. AC response of the proposed floating load output stage
Fig 14. Power diagram with rectangular wave of frequency 50khz with load
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
response of the proposed floating load output stage
Fig 14. Power diagram with rectangular wave of frequency 50khz with load
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
21
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
Fig 15. Layout diagram of proposed floating output node of buffer amplifier
REFERENCES
[1] R. Ito, T. Itakura, and H. Minamizaki, “A class AB amplifier for LCD driver,” 2007 Symposium on
VLSI Circuits Digest of Technology Papers, 14
[2] M-C Weng and J-C Wu, “A Compact Low
Driver,” IEICE Trans. Electron., Vol. E85
[3] G-T Hong and C-H Shen, “A low Offset High Voltage Swing Rail
LCD Driver,” 2007 IEEE Conference on Electron Devices and Solid
1025- 1030, 20-22 Dec. 2007.
[4] Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power
Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE
ISSCC pp.244-245, 1994.
[5] Chih-Wen Lu and Chung Len Lee “A Low Power High Speed Class
Panel Display Application”, IEEE Transactions on VLSI Systems, Vol 10, No. 2, April 2002.
[6] Chih-Wen Lu “A Low Power High Speed Class
Application”, Digest of SID, 2002.
[7] Fan You, S.H.K. Embabi and Edgar Sanchez
with Quiescent Current Control,” IEEE Journal of Solid
920, June 1998.
[8] Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power
Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE
Journal of Solid-State and Circuits. Vol. 29, No.12 December 19
[9] Klaas-Jan de Langen, Johan H. Huijsing, “Compact
Amplifiers Cells for VLSI,” IEEE Journal of Solid
October1998.
[10] A. Torralba, R.G. Carvajal, J. Martinez
low voltage CMOSop-amps with accurate quiescent
Vol. 36, No. 21, 12th October 2000.
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
Fig 15. Layout diagram of proposed floating output node of buffer amplifier
Minamizaki, “A class AB amplifier for LCD driver,” 2007 Symposium on
VLSI Circuits Digest of Technology Papers, 14-16 June 2007, pp. 148-149.
C Wu, “A Compact Low-Power Rail-to-Rail Class-B Buffer for LCD Column
ctron., Vol. E85-C, No. 8 August, pp. 1659-1663, 2002.
H Shen, “A low Offset High Voltage Swing Rail-to Rail Buffer Amplifier with for
LCD Driver,” 2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007 EDSSC, pp.
22 Dec. 2007.
Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power
Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE
u and Chung Len Lee “A Low Power High Speed Class-AB Buffer Amplifier for Flat
Panel Display Application”, IEEE Transactions on VLSI Systems, Vol 10, No. 2, April 2002.
Wen Lu “A Low Power High Speed Class-AB Buffer Amplifier for Flat Panel Displ
Application”, Digest of SID, 2002.
Fan You, S.H.K. Embabi and Edgar Sanchez-Sinencio, “Low-Voltage Class AB Output Amplifiers
with Quiescent Current Control,” IEEE Journal of Solid-State and Circuits. Vol.33, No.6, pp. 915
Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power
Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE
State and Circuits. Vol. 29, No.12 December 1994.
Jan de Langen, Johan H. Huijsing, “Compact-Low-VoltagePower-Efficient Operational
Amplifiers Cells for VLSI,” IEEE Journal of Solid-State and Circuits. Vol. 33, No.10, pp. 1482
A. Torralba, R.G. Carvajal, J. Martinez-Heredia and J.Ramirez-Angulo,” Class AB output stage for
amps with accurate quiescent-current-control,” ELECTRONICS LETTERS
Vol. 36, No. 21, 12th October 2000.
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
22
Minamizaki, “A class AB amplifier for LCD driver,” 2007 Symposium on
B Buffer for LCD Column
to Rail Buffer Amplifier with for
State Circuits, 2007 EDSSC, pp.
Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power-
Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE
AB Buffer Amplifier for Flat
Panel Display Application”, IEEE Transactions on VLSI Systems, Vol 10, No. 2, April 2002.
AB Buffer Amplifier for Flat Panel Display Driver
Voltage Class AB Output Amplifiers
State and Circuits. Vol.33, No.6, pp. 915-
Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power-
Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE
Efficient Operational
State and Circuits. Vol. 33, No.10, pp. 1482-1496,
Angulo,” Class AB output stage for
control,” ELECTRONICS LETTERS
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015
23
[11] Joongsik Kih, Byungsoo Chang, Deog-Kyoon Jeong, and Wonchan Kim, “Class-AB Large-Swing
CMOS Buffer Amplifier with Controlled Bias Current,” IEEE Journal of Solid-State and Circuits.
Vol. 28, No.12, pp. 1350-1353, December 1993.
[12] Davide Marano, Gaetano Palumbo, and Salvatore Pennisi, "Low-Power Dual-Active Class-AB Buffer
Amplifier with Self-Biasing Network for LCD Column Drivers," ISCAS 2010, Paris, pp. 2832-2835.
[13] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001, pp. 471- 479.
[14] R.J baker, CMOS Mixed-Signal Circuit Design. New York:IEEE Press Wiley-Interscience,
2002,pp.334-339.
[15] A. Erhart and D. McCartney, “Charge conservation implementation in an ultra-low power AMLCD
column driver utilizing pixel inversion,” in SID Int. Symp., Seminar & Exhibition Dig. Tech. Papers,
May 1997,pp. 23–26.
[16] J.-S. Kim, D.-K. Jeong, and G. Kim, “A multi-level multi-phase charge-recycling method for low-
power AMLCD column drivers,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 74–84, Jan. 2000.
[17] Y.-S. Son, J.-H. Kim, H.-H. Cho, J.-P. Hong, J.-H. Na, D.-S. Kim, D.-K. Han, J.-C. Hong, Y.-J. Jeon,
and G.-H. Cho, “A column driver with low-power area-efficient push-pull buffer amplifiers for active
matrix LCDs,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2007, pp. 142–
143.
[18] W.-J. Huang, S. Nagayasu, and S.-I. Liu, “A rail-to-rail class-B buffer with DC level-shifting current
mirror and distributed miller compensation for LCD column drivers,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 58, no. 8, pp. 1761–1772, Aug. 2011.
AUTHORS
Dr. R.K. Baghel
Designation: Professor MANIT Bhopal
Qualification: B.E, M.Tech, Ph.D
Research Interest: Low Power Analog circuit design ,LCD driver circuit design mixed
mode analog circuit, Low power Operational amplifier, Data converter
Hari shanker srivastava received B.Tech degree 2007 and M.Tech degree 2010 from
MANIT Bhopal. He is working towards the Ph.D degree. His research interest is
mixed mode analog circuit design and reversible logic design

More Related Content

PDF
Design of Low Voltage and High Speed Double-Tail Dynamic Comparator for Low P...
PDF
Analysis and design_of_a_low-voltage_low-power[1]
PDF
Design of High-Speed Dynamic Double-Tail Comparator
DOC
Double tail comparator
PPT
Analysis and design of a low voltage and low power double tail comparator
PDF
High Speed, Low Offset, Low Power, Fully Dynamic Cmos Latched Comparator
PDF
Performance analysis of High Speed ADC using SR F/F
PDF
2 twofold mode series echoing dc dc converter for ample load
Design of Low Voltage and High Speed Double-Tail Dynamic Comparator for Low P...
Analysis and design_of_a_low-voltage_low-power[1]
Design of High-Speed Dynamic Double-Tail Comparator
Double tail comparator
Analysis and design of a low voltage and low power double tail comparator
High Speed, Low Offset, Low Power, Fully Dynamic Cmos Latched Comparator
Performance analysis of High Speed ADC using SR F/F
2 twofold mode series echoing dc dc converter for ample load

What's hot (20)

PDF
Experiment 5
PDF
RESEARCH EXPLORER -2 ISSUE
PDF
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture
PDF
Amplificadores.py5 aal
PDF
CapSense Capacitive Sensors Sigma Delta Algorithm
PDF
Agostinho2008
PDF
Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic
PDF
Parviz-PCIM99
PDF
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...
PDF
2002 15
PDF
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...
PPTX
Presentazione standard1
PDF
Minimum Mismatch of Current in Fully Differential Charge Pump for Integer N- ...
PDF
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...
PDF
FinalReport
PDF
Iaetsd an mtcmos technique for optimizing low
PDF
The effect of ripple steering on control loop stability for ac cm pfc boost c...
PDF
G43064245
PDF
C010311320
Experiment 5
RESEARCH EXPLORER -2 ISSUE
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture
Amplificadores.py5 aal
CapSense Capacitive Sensors Sigma Delta Algorithm
Agostinho2008
Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic
Parviz-PCIM99
IRJET - Wireless Power Transfer System using Pulse Density Modulation based F...
2002 15
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...
Presentazione standard1
Minimum Mismatch of Current in Fully Differential Charge Pump for Integer N- ...
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...
FinalReport
Iaetsd an mtcmos technique for optimizing low
The effect of ripple steering on control loop stability for ac cm pfc boost c...
G43064245
C010311320
Ad

Viewers also liked (17)

PDF
An operational amplifier with recycling folded cascode topology and adaptive ...
PDF
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGA
PDF
An efficient multi resolution filter bank based on da based multiplication
PDF
Tracking cancer patients medical history using wireless emerging technology ...
PDF
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...
PDF
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...
PPTX
Elements to Consider When Checking Onsite and Offsite Factors
PDF
Design of a novel current balanced voltage controlled delay element
PDF
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATION
PDF
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...
PDF
ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODEL
PDF
The Road to Traffic Attraction
PDF
A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUIT
PPTX
PDF
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLER
PDF
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...
An operational amplifier with recycling folded cascode topology and adaptive ...
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGA
An efficient multi resolution filter bank based on da based multiplication
Tracking cancer patients medical history using wireless emerging technology ...
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...
Elements to Consider When Checking Onsite and Offsite Factors
Design of a novel current balanced voltage controlled delay element
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATION
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...
ANALOG MODELING OF RECURSIVE ESTIMATOR DESIGN WITH FILTER DESIGN MODEL
The Road to Traffic Attraction
A NEW LOW VOLTAGE P-MOS BULK DRIVEN CURRENT MIRROR CIRCUIT
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLER
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...
Ad

Similar to Dynamic floating output stage for low power buffer amplifier for lcd application (20)

PDF
Compact low power high slew-rate cmos buffer amplifier with power gating tech...
PDF
Design of Low Voltage Low Power CMOS OP-AMP
DOC
Physical designing of low power operational amplifier
PDF
A Low Noise Two Stage Operational Amplifier on 45nm CMOS Process
PDF
Design and analysis of a two stage miller compensated
PDF
International Journal of Computational Engineering Research(IJCER)
PDF
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...
PDF
An analysis of pfc converter with high speed dynamic
PDF
An analysis of pfc converter with high speed dynamic
PDF
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...
PDF
Design and analysis of low power pseudo differential
PDF
Comparison of parallel summation and weak
PDF
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...
PDF
IRJET-Design of Charge Pump for PLL with Reduction In Current Mismatch and Va...
PDF
A fuzzy logic controlled dc dc converter for an
PDF
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...
PDF
Journal article
PDF
HARMONIC MITIGATION USING D STATCOM THROUGH A CURRENT CONTROL TECHNIQUE
PDF
A High-Swing OTA with wide Linearity for design of self-tunable linear resistor
PDF
A High-Swing OTA with wide Linearity for design of self-tunable linear resistor
Compact low power high slew-rate cmos buffer amplifier with power gating tech...
Design of Low Voltage Low Power CMOS OP-AMP
Physical designing of low power operational amplifier
A Low Noise Two Stage Operational Amplifier on 45nm CMOS Process
Design and analysis of a two stage miller compensated
International Journal of Computational Engineering Research(IJCER)
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...
An analysis of pfc converter with high speed dynamic
An analysis of pfc converter with high speed dynamic
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...
Design and analysis of low power pseudo differential
Comparison of parallel summation and weak
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...
IRJET-Design of Charge Pump for PLL with Reduction In Current Mismatch and Va...
A fuzzy logic controlled dc dc converter for an
A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for H...
Journal article
HARMONIC MITIGATION USING D STATCOM THROUGH A CURRENT CONTROL TECHNIQUE
A High-Swing OTA with wide Linearity for design of self-tunable linear resistor
A High-Swing OTA with wide Linearity for design of self-tunable linear resistor

Recently uploaded (20)

PDF
Building Integrated photovoltaic BIPV_UPV.pdf
PDF
MIND Revenue Release Quarter 2 2025 Press Release
PPTX
Understanding_Digital_Forensics_Presentation.pptx
PPTX
Detection-First SIEM: Rule Types, Dashboards, and Threat-Informed Strategy
DOCX
The AUB Centre for AI in Media Proposal.docx
PDF
Diabetes mellitus diagnosis method based random forest with bat algorithm
PPTX
Effective Security Operations Center (SOC) A Modern, Strategic, and Threat-In...
PPTX
Big Data Technologies - Introduction.pptx
PDF
7 ChatGPT Prompts to Help You Define Your Ideal Customer Profile.pdf
PPTX
Cloud computing and distributed systems.
PDF
The Rise and Fall of 3GPP – Time for a Sabbatical?
PDF
Electronic commerce courselecture one. Pdf
PDF
Architecting across the Boundaries of two Complex Domains - Healthcare & Tech...
PDF
Spectral efficient network and resource selection model in 5G networks
PPTX
sap open course for s4hana steps from ECC to s4
PPTX
Programs and apps: productivity, graphics, security and other tools
PDF
Encapsulation_ Review paper, used for researhc scholars
PDF
Agricultural_Statistics_at_a_Glance_2022_0.pdf
PDF
Machine learning based COVID-19 study performance prediction
PDF
NewMind AI Weekly Chronicles - August'25 Week I
Building Integrated photovoltaic BIPV_UPV.pdf
MIND Revenue Release Quarter 2 2025 Press Release
Understanding_Digital_Forensics_Presentation.pptx
Detection-First SIEM: Rule Types, Dashboards, and Threat-Informed Strategy
The AUB Centre for AI in Media Proposal.docx
Diabetes mellitus diagnosis method based random forest with bat algorithm
Effective Security Operations Center (SOC) A Modern, Strategic, and Threat-In...
Big Data Technologies - Introduction.pptx
7 ChatGPT Prompts to Help You Define Your Ideal Customer Profile.pdf
Cloud computing and distributed systems.
The Rise and Fall of 3GPP – Time for a Sabbatical?
Electronic commerce courselecture one. Pdf
Architecting across the Boundaries of two Complex Domains - Healthcare & Tech...
Spectral efficient network and resource selection model in 5G networks
sap open course for s4hana steps from ECC to s4
Programs and apps: productivity, graphics, security and other tools
Encapsulation_ Review paper, used for researhc scholars
Agricultural_Statistics_at_a_Glance_2022_0.pdf
Machine learning based COVID-19 study performance prediction
NewMind AI Weekly Chronicles - August'25 Week I

Dynamic floating output stage for low power buffer amplifier for lcd application

  • 1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 DOI : 10.5121/vlsic.2015.6102 9 DYNAMIC FLOATING OUTPUT STAGE FOR LOW POWER BUFFER AMPLIFIER FOR LCD APPLICATION Hari shanker srivastava and Dr.R.K Baghel Department of Electronics and Communication MANIT Bhopal ABSTRACT This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 µA for 30 pF capacitance, the settling time calculated as 4.5µs, the slew rate obtained as 5V/µs and area on chip is 30×72µ݉ଶ . KEYWORDS Liquid crystal display (LCD) ,column driver, row driver, gamma correction, class AB output stage 1. INTRODUCTION With increasing demand of low-power portable LCD panel there was hard-core research to develop it as with the low-power means we have to decrease the static loss of the component or the blocks used in the driving scheme of the LCD panel, the driving scheme of LCD panel is shown in figure 1, which consists of source driver circuits (column driver), gate driver circuits(row driver), the reference voltages, timing controller's, gamma correction circuits, column driver is used to drive a pixel with required colored information and row driver used to refresh a pixel which required refreshing rate.[1,2] The column driver as shown in fig.2 contains input registers, shift registers, level shifters, digital to analog converter and buffer amplifiers. The column driver which is important to achieve the high resolution, high-speed, and low power dissipation among these output buffers is the key to determine the speed, resolution, and power consumption each pixel is derived by a buffer amplifier which is either positive polarity or negative polarity to drive the alternate pixel.
  • 2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 10 Fig 1.Block diagram of LCD panel Fig 2.Column driver architecture of LCD
  • 3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 11 Fig 3.Architecture of an R_DAC based column Fig 4. Dot inversion method to drive There are four driving schemes for LCD panels these are row inversion, column inversion, frame inversion and dot inversion method, dot inversion method is best to drive a particular pixel to remove cross talk figure.4 shows its driving scheme adjacent pixel is driven by either a positive polarity buffer or by negative polarity buffer with due respect to common voltage, this will improve the lifetime of the liquid crystal.[3],[4],[5].The figure.4 shows a driving method of column driver to drive a pixel each adjacent pixels are driven by positive and negative polarity buffer [8-11]. In proposed buffer amplifier a single buffer which contain NMOS & PMOS differential pair, PMOS buffer has large discharge capability and NMOS has large charge capability are used to drive the adjacent pixel to follow the dot inversion technique. A floating output stage is used to control the biasing current of output stage using aspect ratio of MOS used in output stage. 2. FREQUENCY ANALYSIS OF TWO STAGE BUFFER To drive high capacitive and resistive load of the pixel a class AB output stage is best suited for the column driver line. For low offset voltage we need high open loop gain of buffer amplifier, two-stage amplifier are generally used to drive the pixel, amplifier requires compensation capacitor for the stability as the phase margin of the operation amplifier depend upon the compensation capacitor, the slew rate is also depends on compensation capacitor. As some buffers adopt output node to get the stability without using Miller capacitance, some uses charge
  • 4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 12 conservation technique to reduce the dynamic power loss without Miller capacitance. These buffer suffers from charge storage problem as during scanning off time of row driver's the columns lines are for a small duration of time is isolated from the pixels to refresh formation at buffer quickly, so we need a capacitor which is fulfilled by compensation capacitor so those buffers which are without compensation capacitors have a problem that they can't refresh there information within the refresh time. As the proposed buffer has two-stage with the Miller capacitor for the compensation is used in design. The figures.5 shows the equivalent circuit of two stage operational amplifier with output load resistance and capacitance. ࡾࡸ ࡯ࡸ Fig 5. Small signal model of proposed buffer amplifier Figure 5 shows small signal equivalent diagram of proposed amplifier for two stage under open loop, ݃௠ଵ & ݃௠ଶ are the transconductance, ܴଵ & ܴଶ are the output resistance, ‫ܥ‬ଵ & ‫ܥ‬ଶ are the open loop parasitic capacitance of the first and second stages, ‫ܥ‬௖ is the miller capacitance for phase compensation and ܴ௅& ‫ܥ‬௅are the resistive and capacitive load. The transfer function of the amplifier is calculated using current equation:- using current equation at input node: ݃௠ଵܸ௜ௗ + ܸଵ ܴଵ + ܵ‫ܥ‬ଵܸଵ + ሺܸଵ − ܸ଴ሻܵ‫ܥ‬஼ = 0 ܸଵ ቂ ଵ ோభ + ܵሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻቃ = ܸܵ଴‫ܥ‬஼ − ݃௠ଵܸ௜ௗ (1) using current equation at output node: ݃௠ଶܸଵ + ܸ଴ ܴଶ + ܵ‫ܥ‬ଶܸ଴ + ሺܸ଴ − ܸଵሻܵ‫ܥ‬஼ + ܸ଴ ቀܴ௅ + 1 ܵ‫ܥ‬௅ ቁ = 0 ܸ଴ ൤ 1 ܴଶ + ܵሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ + ܵ‫ܥ‬௅ 1 + ܴܵ௅‫ܥ‬௅ ൨ = ܸଵሺܵ‫ܥ‬஼ − ݃௠ଶሻ ሺ2ሻ Put value of ܸଵfrom equation 1 to equation 2 we get,
  • 5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 13 ܸ଴ ܸ௜ௗ = ݃௠ଵ݃௠ଶܴଵܴଶ ൬1 − ܵ‫ܥ‬஼ ݃௠ଶ ൰ሺ1 + ܴܵ௅‫ܥ‬௅ሻ 1 + ‫ܣ‬ଵܵ + ‫ܣ‬ଶܵଶ + ‫ܣ‬ଷܵଷ ሺ3ሻ ‫ܣ‬ଵ = ܴଵሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ + ܴ௅‫ܥ‬௅ + ܴଶሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ + ‫ܥ‬௅ܴଶ + ܴଵܴଶ݃௠ଶ‫ܥ‬஼ ‫ܣ‬ଶ = ܴଵܴ௅‫ܥ‬௅ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ + ܴଵܴଶሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ + ܴଵܴଶ‫ܥ‬௅ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ + ‫ܥ‬௅ܴ௅ܴଶሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ + ܴଵܴଶ‫ܥ‬஼ሾ‫ܥ‬஼ − ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ݃௠ଶܴଵሿ ‫ܣ‬ଷ = ܴଵܴଶܴ௅‫ܥ‬௅ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻሺ‫ܥ‬ଶ + ‫ܥ‬஼ሻ + ܴଵ ଶ ܴଶ‫ܥ‬஼ ଶ ሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻ As from equation 3 it show 3rd order transfer function ‫ܣ‬଴ሺܵሻ = ‫ܣ‬ௗ௖ ቀ1 + ܵ ߱௓ଵ ቁ ቀ1 + ܵ ߱௓ଶ ቁ ቀ1 + ܵ ߱௉ଵ ቁ ቀ1 + ܵ ߱௉ଶ ቁ ቀ1 + ܵ ߱௉ଷ ቁ to solve the 3rd order transfer function using dominant pole concept, the characteristic equation is written as: 1 + ‫ܣ‬ଵܵ + ‫ܣ‬ଶܵଶ + ‫ܣ‬ଷܵଷ = 0 ≈ ‫ܣ‬ଵܵ + ‫ܣ‬ଶܵଶ + ‫ܣ‬ଷܵଷ = 0 ≈ ‫ܣ‬ଵܵሺ1 + ‫ܣ‬ଶ ‫ܣ‬ଵ ܵ + ‫ܣ‬ଷ ‫ܣ‬ଵ ܵଶ ሻ = 0 ߱௉ଵ ≅ − 1 ‫ܣ‬ଵ ߱௉ଶ ≅ ‫ܣ‬ଵ ‫ܣ‬ଶ ߱௉ଷ = 1 ܲଶ ‫ܣ‬ଵ ‫ܣ‬ଶ ‫ܣ‬ௗ௖ = ݃௠ଵ݃௠ଶܴଵܴଶ ߱௉ଵ ≅ 1 ܴଵܴଶ݃௠ଶ‫ܥ‬஼ + ‫ܥ‬௅ܴଶ ߱௉ଶ ≅ 1 ሾሺ‫ܥ‬ଵ + ‫ܥ‬஼ሻܴ௅ሿ
  • 6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 14 ߱௉ଷ ≅ ݃௠ଶ‫ܥ‬஼ + ‫ܥ‬௅ ܴଵ ൗ ‫ܥ‬஼‫ܥ‬௅ ߱௓ଵ = ି௚೘మ ஼಴ and ߱௓ଶ = ଵ ோಽ஼ಽ the unity gain frequency(߱௧)= ‫ܣ‬ௗ௖ ߱௉ଵ ߱௧ = ݃௠ଵ݃௠ଶ ‫ܥ‬஼݃௠ଶ + ‫ܥ‬௅ ܴଵ ൗ taking 3rd pole very far away from unity gain bandwidth so it does not affect the phase margin so ߱௓ଶ will compensate for ߱௉ଷ so the transfer function act like 2nd order transfer function, ‫ܣ‬଴ሺܵሻ = ‫ܣ‬ௗ௖ ቀ1 + ܵ ߱′௓ଵ ቁ ቀ1 + ܵ ߱′௉ଵ ቁ ቀ1 + ܵ ߱′௉ଶ ቁ where ߱′௓ଵ = ି௚೘మ ஼಴ ߱′௉ଵ ≅ 1 ܴଵܴଶ݃௠ଶ‫ܥ‬஼ ߱௉ଶ ≅ ݃௠ଶ ሾ‫ܥ‬ଶሿ Phase margin of the amplifier is as: < ‫ܣ‬଴ሺܵሻ = ‫݊ܽݐ‬ିଵ ൬ ߱ ߱′௓ଵ ൰ − ‫݊ܽݐ‬ିଵ ൬ ߱ ߱′௉ଵ ൰ − ‫݊ܽݐ‬ିଵ ൬ ߱ ߱′௉ଶ ൰ as ω=GBW(taken this as a frequency range) < ‫ܣ‬଴ሺܵሻ = −‫݊ܽݐ‬ିଵ ൬ GBW ߱′௓ଵ ൰ − ‫݊ܽݐ‬ିଵ ൬ GBW ߱′௉ଵ ൰ − ‫݊ܽݐ‬ିଵ ൬ GBW ߱′௉ଶ ൰ under condition ߱′௓ଵ ≥ 10‫ܹܤܩ‬ < ‫ܣ‬଴ሺܵሻ = ‫݊ܽݐ‬ିଵ ൬ GBW ߱′௓ଵ ൰ − ‫݊ܽݐ‬ିଵሺ‫ܣ‬ௗ௖ ሻ − ‫݊ܽݐ‬ିଵ ൬ GBW ߱′௉ଶ ൰ as ‫ܣ‬ௗ௖ is very higher value so ‫݊ܽݐ‬ିଵሺ‫ܣ‬ௗ௖ ሻ=90଴
  • 7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 15 < −180଴ − ܲ‫ܯ‬ = ‫݊ܽݐ‬ିଵ ൬ 1 10 ൰ − 90଴ − ‫݊ܽݐ‬ିଵ ൬ GBW ߱′௉ଶ ൰ PM=90଴ -‫݊ܽݐ‬ିଵ ቀ ୋ୆୛ ఠ′ುమ ቁ − ‫݊ܽݐ‬ିଵ ቀ ୋ୆୛ ఠ′ೋభ ቁ For phase margin of 60଴ and ߱′௓ଵ = 10‫ܹܤܩ‬ ߱′௉ଶ = 2.2 ‫ܹܤܩ‬ ߱′௉ଶ = 2.2 ‫ܹܤܩ‬ ‫ܥ‬஼ = .22‫ܥ‬௅ and ݃௠ଶ = 10݃௠ଵ As seen that with higher value ݃௠ଶ the value of ‫ܥ‬஼ we will get become smaller but it leads to large current flow in output stage and hence more static power loss occurs in amplifier as with large value of ‫ܥ‬஼ it accurse large area on chip, if we chose load resistance and capacitance too large than open loop zero come in picture and then, PM=90଴ − ‫݊ܽݐ‬ିଵ ቀ ୋ୆୛ ఠ′ೋభ ቁ then ௚೘మ ௚೘భ = ଵ ୲ୟ୬ሺଽ଴బି௉ெሻ Fig 6. Open loop frequency response of two-stage opam with & without load capacitance and resistance 3. PROPOSED BUFFER AMPLIFIER WITH DYNAMIC FLOATING To reduce the static power loss we combined N- type and P-type differential pair with dynamic floating concept to reduce the current flowing at the output stage, two floating bias current ln1 and ln2 are used to charge and discharge the output node in combination with lb1 and lb2, during transition phase from low to high Mp-bias will provide extra current to charge the capacitive load and during high to low Mn-bias will sink the extra current to discharge the capacitive load quickly this is the methodology for which we quickly charge and discharge the output load without increasing the static current that flows through the complementary common source
  • 8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 16 amplifier M01 and M02. The two output are isolated by the combination of 6 transistors as shown in the figure.7 Mn-bias, Mn-bias,MDN1, MDN2, MDP1 and MDP2 for same rising and falling time ln1=ln2,lb1=lb2 lb1 = lb2 = ln1൤ 1 + ൫ௐ ௅ൗ ൯ ಾವಿమ ൫ௐ ௅ൗ ൯ ಾವಿభ + ൫ௐ ௅ൗ ൯ ಾವುమ ൫ௐ ௅ൗ ൯ ಾವುభ ൨ The schematic of the proposed buffer is shown in the figure. 8,M1-M5 shows NMOS differential pair,M6-M10 shows PMOS differential pair,C1-C4 shows miller capacitance, the biasing current of NMOS and PMOS pair is Ib as M01 and M02 are mirrored from M5 and M10 which is Ib/2 current that will flow, as seen the output stage biased by dynamic floating and 2 single-stage differential pair, the circuit will suffer from output DC offset voltage which is removed by proper sizing as ൫ܹ ‫ܮ‬ൗ ൯ ெ଴ଵ ൫ܹ ‫ܮ‬ൗ ൯ ସ = ൫ܹ ‫ܮ‬ൗ ൯ ெ଴ଶ ൫ܹ ‫ܮ‬ൗ ൯ ଽ = ln1 ቎1 + ൫ܹ ‫ܮ‬ൗ ൯ ெ஽ேଶ ൫ܹ ‫ܮ‬ൗ ൯ ெ஽ேଵ + ൫ܹ ‫ܮ‬ൗ ൯ ெ஽௉ଶ ൫ܹ ‫ܮ‬ൗ ൯ ெ஽௉ଵ ቏ To design operational amplifier for LCD the following requirement should meet according to number of bits or resolution of DAC used in LCD panel[23],The open loop gain will be estimated as ‫ܣ‬ை௅஽஼ ≥ 2ேାଵ Fig 7. Architecture of proposed dynamic floating buffer amplifier
  • 9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 17 Let open loop gain will be 1000 then gain error will be gain error = ଵ .ହ×ଵ଴଴଴ = .0002 ≤ ௏ೝ೐೑ ଶಿశభ so min value of VDD=512× .002 = 1.02 ‫ݐ݈݋ݒ‬ and with specific settling time which should be less than scanning time let it will be 1µs,the gain bandwidth ‫ܹܤܩ‬ ≥ ݈݊2ேାଵ 2ߨ‫ݐ‬௦ for 8 bit the frequency does not exceed 1Mhz. So the design specification for buffer amplifier is DC gain ≥ 1000=60db, VDD=3.3 volt , GBW=1Mhz PM=60o ,CMOS technology 180nm, load capacitance= 30pf and load resistance of 30kΩ. Fig 8. Schematic of proposed dynamic floating buffer amplifier
  • 10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 18 M1 1.5 1ൗ M9 5 1ൗ M01 28 1ൗ M2 1.9 1ൗ M10 5 1ൗ M02 28 1ൗ M3 1.9 1ൗ MPBIAS 4.5 1ൗ C1 1p M4 5 1ൗ MNBIAS 4 1ൗ C2 6p M5 5 1ൗ MDN1 4.5 1ൗ C3 1p M6 2 1ൗ MDN2 9 1ൗ C4 6p M7 25 1ൗ MDP1 8 1ൗ CL 30P M8 25 1ൗ MDP2 4 1ൗ RL 30Ω 4. EXPERIMENTAL RESULT The proposed buffer amplifier is fabricated using a 180nm CMOS technology. The chip area occupied by the buffer is 30×72 µ݉ଶ , fig 9 shows the output with 50kz input square wave with load capacitance of 30pF and 30kΩ resistance, fig 10 shows triangular response of proposed buffer, the slew rate obtained is 4.8v/µs with setting time of 4.5 µs and 4.2 µs for up and down stream of square wave, the biasing current per channel is 5µA. And power consumed by buffer is 72 µw. The simulation results using transient and AC analysis is shown in figure from 9 to15 using cadence spectre simulation tool. 5. CONCLUSION This paper represents a low power buffer amplifier, with low quiescent current with the dynamic floating output node we adjust the output bias current without changing the input differential pair biasing current configuration, according to load capacitance the output current will be varied with the help of floating bias current network. The use-fullness of such type of buffer is, it work as positive and negative type buffer without any switched capacitor network which is used to toggle the differential amplifier in between positive and negative buffer. COMPARISON TABLE This work [1] [2] [3] [4] Process 180nm CMOS .35µmCMOS .35µmCMOS .35µm CMOS .35µm CMOS VDD 3.3 5 3.3 5 Bias current 5µA/per channel 2µA 7.4µA NA 5µA loads 30KΩ, 30pF 10KΩ, 24pF 600pF 400pF 10pF o/p swing 96% NA NA NA NA Settling time 4.5µs 2µs 8µs 1µs .5µs Slew rate 5v/ µs NA NA NA 2v/ µs Area 30×72 µ݉ଶ 22×190µ݉ଶ 100×45µ݉ଶ 86×74 µ݉ଶ .04 m݉ଶ
  • 11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 Fig 9. Simulation result with rectangular wave of frequency 50khz with load Fig 10. Simulation result with rectangular wave of frequency 50khz with two input output International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 Fig 9. Simulation result with rectangular wave of frequency 50khz with load result with rectangular wave of frequency 50khz with two input output International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 19 result with rectangular wave of frequency 50khz with two input output
  • 12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 Fig 11. Simulation result with triangular wave of frequency 50khz with load Fig 12. Simulation result with triangular wave of frequency 50khz with two input output International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 Fig 11. Simulation result with triangular wave of frequency 50khz with load Fig 12. Simulation result with triangular wave of frequency 50khz with two input output International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 20 Fig 12. Simulation result with triangular wave of frequency 50khz with two input output
  • 13. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 Fig 13. AC response of the proposed floating load output stage Fig 14. Power diagram with rectangular wave of frequency 50khz with load International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 response of the proposed floating load output stage Fig 14. Power diagram with rectangular wave of frequency 50khz with load International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 21
  • 14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 Fig 15. Layout diagram of proposed floating output node of buffer amplifier REFERENCES [1] R. Ito, T. Itakura, and H. Minamizaki, “A class AB amplifier for LCD driver,” 2007 Symposium on VLSI Circuits Digest of Technology Papers, 14 [2] M-C Weng and J-C Wu, “A Compact Low Driver,” IEICE Trans. Electron., Vol. E85 [3] G-T Hong and C-H Shen, “A low Offset High Voltage Swing Rail LCD Driver,” 2007 IEEE Conference on Electron Devices and Solid 1025- 1030, 20-22 Dec. 2007. [4] Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE ISSCC pp.244-245, 1994. [5] Chih-Wen Lu and Chung Len Lee “A Low Power High Speed Class Panel Display Application”, IEEE Transactions on VLSI Systems, Vol 10, No. 2, April 2002. [6] Chih-Wen Lu “A Low Power High Speed Class Application”, Digest of SID, 2002. [7] Fan You, S.H.K. Embabi and Edgar Sanchez with Quiescent Current Control,” IEEE Journal of Solid 920, June 1998. [8] Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE Journal of Solid-State and Circuits. Vol. 29, No.12 December 19 [9] Klaas-Jan de Langen, Johan H. Huijsing, “Compact Amplifiers Cells for VLSI,” IEEE Journal of Solid October1998. [10] A. Torralba, R.G. Carvajal, J. Martinez low voltage CMOSop-amps with accurate quiescent Vol. 36, No. 21, 12th October 2000. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 Fig 15. Layout diagram of proposed floating output node of buffer amplifier Minamizaki, “A class AB amplifier for LCD driver,” 2007 Symposium on VLSI Circuits Digest of Technology Papers, 14-16 June 2007, pp. 148-149. C Wu, “A Compact Low-Power Rail-to-Rail Class-B Buffer for LCD Column ctron., Vol. E85-C, No. 8 August, pp. 1659-1663, 2002. H Shen, “A low Offset High Voltage Swing Rail-to Rail Buffer Amplifier with for LCD Driver,” 2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007 EDSSC, pp. 22 Dec. 2007. Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE u and Chung Len Lee “A Low Power High Speed Class-AB Buffer Amplifier for Flat Panel Display Application”, IEEE Transactions on VLSI Systems, Vol 10, No. 2, April 2002. Wen Lu “A Low Power High Speed Class-AB Buffer Amplifier for Flat Panel Displ Application”, Digest of SID, 2002. Fan You, S.H.K. Embabi and Edgar Sanchez-Sinencio, “Low-Voltage Class AB Output Amplifiers with Quiescent Current Control,” IEEE Journal of Solid-State and Circuits. Vol.33, No.6, pp. 915 Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE State and Circuits. Vol. 29, No.12 December 1994. Jan de Langen, Johan H. Huijsing, “Compact-Low-VoltagePower-Efficient Operational Amplifiers Cells for VLSI,” IEEE Journal of Solid-State and Circuits. Vol. 33, No.10, pp. 1482 A. Torralba, R.G. Carvajal, J. Martinez-Heredia and J.Ramirez-Angulo,” Class AB output stage for amps with accurate quiescent-current-control,” ELECTRONICS LETTERS Vol. 36, No. 21, 12th October 2000. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 22 Minamizaki, “A class AB amplifier for LCD driver,” 2007 Symposium on B Buffer for LCD Column to Rail Buffer Amplifier with for State Circuits, 2007 EDSSC, pp. Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power- Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE AB Buffer Amplifier for Flat Panel Display Application”, IEEE Transactions on VLSI Systems, Vol 10, No. 2, April 2002. AB Buffer Amplifier for Flat Panel Display Driver Voltage Class AB Output Amplifiers State and Circuits. Vol.33, No.6, pp. 915- Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, “A Compact Power- Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE Efficient Operational State and Circuits. Vol. 33, No.10, pp. 1482-1496, Angulo,” Class AB output stage for control,” ELECTRONICS LETTERS
  • 15. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.1, February 2015 23 [11] Joongsik Kih, Byungsoo Chang, Deog-Kyoon Jeong, and Wonchan Kim, “Class-AB Large-Swing CMOS Buffer Amplifier with Controlled Bias Current,” IEEE Journal of Solid-State and Circuits. Vol. 28, No.12, pp. 1350-1353, December 1993. [12] Davide Marano, Gaetano Palumbo, and Salvatore Pennisi, "Low-Power Dual-Active Class-AB Buffer Amplifier with Self-Biasing Network for LCD Column Drivers," ISCAS 2010, Paris, pp. 2832-2835. [13] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001, pp. 471- 479. [14] R.J baker, CMOS Mixed-Signal Circuit Design. New York:IEEE Press Wiley-Interscience, 2002,pp.334-339. [15] A. Erhart and D. McCartney, “Charge conservation implementation in an ultra-low power AMLCD column driver utilizing pixel inversion,” in SID Int. Symp., Seminar & Exhibition Dig. Tech. Papers, May 1997,pp. 23–26. [16] J.-S. Kim, D.-K. Jeong, and G. Kim, “A multi-level multi-phase charge-recycling method for low- power AMLCD column drivers,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 74–84, Jan. 2000. [17] Y.-S. Son, J.-H. Kim, H.-H. Cho, J.-P. Hong, J.-H. Na, D.-S. Kim, D.-K. Han, J.-C. Hong, Y.-J. Jeon, and G.-H. Cho, “A column driver with low-power area-efficient push-pull buffer amplifiers for active matrix LCDs,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2007, pp. 142– 143. [18] W.-J. Huang, S. Nagayasu, and S.-I. Liu, “A rail-to-rail class-B buffer with DC level-shifting current mirror and distributed miller compensation for LCD column drivers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 8, pp. 1761–1772, Aug. 2011. AUTHORS Dr. R.K. Baghel Designation: Professor MANIT Bhopal Qualification: B.E, M.Tech, Ph.D Research Interest: Low Power Analog circuit design ,LCD driver circuit design mixed mode analog circuit, Low power Operational amplifier, Data converter Hari shanker srivastava received B.Tech degree 2007 and M.Tech degree 2010 from MANIT Bhopal. He is working towards the Ph.D degree. His research interest is mixed mode analog circuit design and reversible logic design